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SCAN

CJSC "SCAN" has more than 20 years experience in information technologies as a partner and supplier of the world leaders products - manufacturers of computer techniques, communication, test and measurement equipment and EDA/CAD systems. Based on the products of such companies "SCAN" develops and implements complex "turn-key" solutions for electronics industries thus contributing to the development of high technologies and revival of national industry and science.
hacked by "Mr.p@r@dox17"
  • Ethernet demo
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  • SPI demo
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Ethernet MAC 10/100
Ethernet MAC 10/100 is a simple MAC controller with 16-bit application interface and MII interface to PHY. It supports nominal speeds 10 and 100 Mbps. Core handles data written by application into transmit buffer and received from MII into receive buffer. In half-duplex mode collisions handled according to CSMA/CD.
hacked by "Mr.p@r@dox17"
  • Ethernet demo
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Ethernet MAC 10/100/1000
MAC IP Core is an evolution of Ethernet 10/100 IP Core. It has 32-bit interface, set if optional statistics registers (accoring to Clause 5.2 IEEE 802.3-2005), it supports 1Gbps transfer speed. RTL model is FPGA-proven. Also TLM model with set of APIs available on demand to check design compatibility with customers' CPUs.
hacked by "Mr.p@r@dox17"
General Purpose Input / Output
GPIO IP Core is a simple IO controller with set of modes. It has APB/generic application interface and can be configured for any width from 1 to 32 bits. Every bit has it's own direction, function, mode, interrupt enable and interrupt generation control. Core is compatible with DFT rules and fully synchronous. Input register has filters to avoid data metastability.
hacked by "Mr.p@r@dox17"
Serial Peripheral Interface
SPI IP Core is a configurable Master/Slave device on Serial Peripheral interface. It has configurable application interface (APB/generic) with width 8, 16, or 32 bits. In master mode SPI generates SCK clock and selects slave device. Data serially moved from transmit buffer on highest SPI rates. In slave mode data captured on external clock. Core is fully synchronous and compatible with DFT rules.
hacked by "Mr.p@r@dox17"
  • SPI demo
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Universal Asynchronous Receiver Transmitter
UART IP Core has configurable APB/generic application interface. External frequency can be used to get precise interface frequency (2400, 4800, 9600, 19.2к, 38.4к, 57.6к, 115.2к...). Data transfer between application and interface frequency synchronized using FIFO. Core is fully synchronous and compatible with DFT rules. Generic TLM model with APIs available for software development.
hacked by "Mr.p@r@dox17"
Fast Fourier Transform
IP Core for direct and inverse Fourier Transform with fixed point arithmetic. Precision configured via data bus width and multiplication coefficients width. Calculation made on a set of complex points written into RAM. Transform size (number of points) configured statically or dynamically (from 8 to 32768). FFT IP Core has generic user interface with configured data width (5 up ot 31 bits). Core based on 2-points butterfly algorithm.
hacked by "Mr.p@r@dox17"

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